The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor integrated circuit memory device used as a program/data memory device for a microcomputer system.
A microcomputer system includes a microprocessor (or a microcomputer) and a memory device which are interconnected through a system bus. The memory device stores a string of instructions for a program and operand data to be executed and processed by the microprocessor. In operation, the microprocessor makes access to the memory device by use of a program address designating a memory location containing an instruction to be executed, and then fetches and executes the instruction read out of the designated memory location. In the instruction execution, if operand data is required, the microprocessor makes access to the memory device by use of a data address for designating a memory location into which that operand data is stored, and then fetches the operand data from the memory data. The processed resultant data is, if necessary, written into the memory device. The microprocessor again makes access to the memory device by use of a next program address to fetch and execute a next instruction to be executed.
In general, the respective instructions for a program are stored in the successive memory locations of the memory device. The microprocessor executes the respective instructions in the address order, so long as it does not execute such an instruction as a jump or branch instruction causing change in the program sequence flow.
However, the microprocessor in the system employing a conventional memory device always supplies the respective program addresses to the device to fetch the corresponding instructions therefrom, irrespective of those instructions being stored in the successive memory locations of the device. For this reason, a bus cycle for accessing the memory device by use of the program memory is always initiated before each instruction execution, resulting in the restriction of the processing speed. In particular, the system employing an address/data multiplex system bus lowers the processing speed remarkablly.